Logical Effort Calculation

Scan Flip Flop Operation

2 Stage Synchronizer Operation

If Reg.1 does not recover from metastability before Edge 2 (usually the settling time for a FF depends on the process parameter), then an additional flip flop would be needed for the synchronizer. The analysis part of this deals with the MTBF (Mean Time Between Failure) math.

Metastability

ASIC Design Flow

Leakage Currents in MOSFETS

Here is a figure that shows the different leakage currents in a MOSFET (A picture IS worth a 1000 words!!!)

4 Bit Ripple Carry Adder

A Simple 4 Bit Ripple Carry Adder is shown below. It is not the most efficient adder because the higher stages in the cascade have to wait for the previous stage to compute Carry Out bit.

Half Adder, Full Adder

Two of the most common Arithmetic Logic Circuits – HA and FA, are shown below.

Master Slave D Flip Flop – Positive or Negative Edge Triggered?

D Latch, D Flip Flop Using MUX

Here is a method to implement a D Latch using a Mux

We can use 2 such above shown modules to implement a D Flip Flop