1. Synchronous Set D Flip Flop
module async_set_dff (clk, d, set, q);
input clk, d, set;
output q;
reg q;
always @ (posedge clk)
begin
if (set)
q <= 1′ b1;
else
q <= d;
end
endmodule
2. Synchronous Reset D Flip Flop
module async_reset_dff (clk, d, reset, q);
input clk, d, reset;
output q;
reg q;
always @ (posedge clk)
begin
if (set)
q <= 1′ b0;
else
q <= d;
end
endmodule
3. Synchronous Set-Reset D Flip Flop
module async_set_reset_dff (clk, d, set, q);
input clk, d, set, reset;
output q;
reg q;
always @ (posedge clk)
begin
if (set)
q <= 1′ b1;
else if (reset)
q <= 1′ b0;
else
q <= d;
end
endmodule
allthingsvlsi 