Logical Effort Calculation

FPGA Vs ASIC – A few key differences

Active again!!!

 

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Ash

Charging, Discharging a Capacitor

Yet another PSpice simulation demonstrating Capacitor charging and discharging (I and V waveforms)

Scan Flip Flop Operation

Stretching Horizons!?

Hi viewers,

I am creating a profile on Facebook – Allthings Vlsi, so that the Blog posts can be accessed from the Faceboon profile. Am just trying something new here. Looking forward to see how it works out!

Cheers

Ash

Why CMOS Logic Should Always Have Vdd Level Input?

There are several Logic Design Topologies that supply a output voltage less than Vdd level (Pass Transistor Topology for example). If these outputs are fed into a CMOS circuit (to the Gate terminal), there are a few issues that arise with reference to Voltage and Current.

i) VOLTAGE ISSUE: The reduced voltage level at the input might be mistaken by the CMOS circuit to be a logic 0 instead of a logic 1. To fix this issue, the switching threshold of the CMOS circuit should be pushed to a lower level so that it can recognize a lower voltage as logic 1. This entails increasing the Width of PMOS – Wp, so much more than Wn – the Width of NMOS (even beyond the sizing for equal rise and fall times)

ii) CURRENT ISSUE: The reduced voltage level at its inputs lead to a situation where the PMOS device is not totally shut down. Eg. Let the Vin = 4.3 V and Vdd = 5 V. For PMOS, Vgs = Vg – Vs = 4.3 – 5 = – 0.7 V, which is around Vt for PMOS and hence its not completely shut down and this causes a increase in Isc compared to the case when Vin = Vdd. This is explained in the waveforms shows below.

I simulated an Inverter Circuit using PSpice Demo Version with its rudimentary MOSFET transistors (so I don’t know its Vt). The following are the waveforms that I got after simulating with Case (i) Vin = 5 V and Case (ii) Vin = 4.3 V. In both cases Vdd = 5 V

This simulation makes us understand that in order to use logic styles like Pass Transistor Logic, one need to use additional devices for level restoration so that the output voltage level is same as Vdd .Hope this gives you a deeper insight into CMOS Design.

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Clock Skew

Here is one of several topics I intend to write regarding Timing in VLSI.

Verilog Event Queue – Which Statement is Executed First?

“Given a set of verilog statements, which of them are executed first?”. The answer can be based on the verilog event queue shown below.

Capacitors – Series and Parallel Equivalents – A Deeper Look!

Most of us know the equivalent capacitance formulas for the series and parallel connections. I found a piece online where the why and how the formulas came to be was explained quiet impressively and I thought I would make a posting of it.

Interconnect Delay Reduction Using Buffer Insertion

Ever wondered how the propagation delay of an interconnect is reduced by inserting buffers in between? Here is an explanation.